Application Design of Wavelet Transform System Based on FPGA

Compared with the traditional Fourier transform, wavelet transform is a multi-scale signal analysis method with good time-frequency localization characteristics. It is very suitable for analyzing the transient and time-varying characteristics of non-stationary signals. This is exactly the analysis of EEG. What is needed, many lesions in EEG are manifested in transient form.

1 Introduction

EEG (Electroencephalograph) is a basic physiological signal of the human body, which has important clinical diagnosis and medical value. Nan Yu’s EEG signal itself has the characteristics of non-stationary randomness, so it is quite difficult to filter it in real time. Since Berger discovered EEG signals in 1929, people have used a variety of digital signal processing techniques to process and analyze EEG signals. Because the filters used in traditional filtering and denoising methods generally have low-pass characteristics, classical filtering methods are used to remove non-stationary signals. Noise, reduce noise, broaden the waveform, and smooth the sudden peak components in the signal, but may lose the important information carried by these sudden changes. Fourier spectrum analysis is only a pure frequency analysis method. This method is for time-varying non-stationary The EEG signal is invalid.

Compared with the traditional Fourier transform, wavelet transform is a multi-scale signal analysis method with good time-frequency localization characteristics. It is very suitable for analyzing the transient and time-varying characteristics of non-stationary signals. This is exactly the analysis of EEG. What is needed, many lesions in EEG are manifested in transient form. Only by combining time and frequency processing, can we achieve better results. However, the wavelet decomposition only decomposes the low frequency part of the last decomposition each time, and does not decompose the high frequency part, so the resolution of the high frequency band is poor. The wavelet packet decomposition is a more detailed method of decomposing and reconstructing signals from wavelet decomposition. It not only decomposes the low-frequency part, but also decomposes the high-frequency part twice, which can well adjust the frequency resolution to It is consistent with the rhythm characteristics of EEG, so wavelet packet decomposition has better filtering characteristics. If the wavelet packet method is introduced into EEG signal analysis. Not only can it overcome the shortcomings of traditional EEG analysis. The Mallat algorithm can also be improved to analyze the deficiencies in the actual EEG.

In the past, the digital processing of EEG signals was realized by a general-purpose PC or a single-chip computer, which had disadvantages such as poor real-time performance. Subsequently, FPGA-based wavelet transform has emerged in the digital processing of EEG signals, and its real-time performance is good. DSP Builder combines the algorithm development, simulation and verification functions of Matlab/Simulink design simulation tools with the HDL synthesis, simulation and verification functions of Quartus II software to provide a good platform for wavelet transform FPGA.

2 One-dimensional discrete wavelet (1D-DWT) Mallat improved algorithm

Multi-resolution analysis is the core theory of wavelet analysis, and its Mallat algorithm is a common algorithm for signal wavelet decomposition and reconstruction. The decomposition and reconstruction formulas of the orthogonal wavelet are determined by the scaling equation coefficients of the scaling function. Assume that the two-scale equation for constructing the scaling function φ

Application Design of Wavelet Transform System Based on FPGA

Since φ(-t) and φ(ts) are multi-resolution analysis scaling functions for constructing orthogonal wavelets, h(n) in the above decomposition and reconstruction formula can be selected as h(-n) or h(ns). . For the convenience of discussion and without loss of generality, the above decomposition formula and reconstruction formula can be rewritten as:

Application Design of Wavelet Transform System Based on FPGA

Then c0(k)=c0(k-2N-1), the signal obtained by equation (13) is the delay of the signal obtained by equation (12). Since the sequences h(n) and g(n) are causal sequences, the filter corresponding to equation (13) is a causal filter. Use equations (7) and (8) to continue decomposing the low-frequency component or low-frequency component and high-frequency component of the signal. Multi-level decomposition or wavelet packet decomposition is possible.

3 Design and implementation of wavelet transform based on DSP Builder

Considering the short-term nature of transient pulse signals, the Daubenchies wavelet with tight support is selected as the analysis wavelet, which is conducive to highlighting the characteristics of the transient signal. The DB wavelet function has good orthogonality and tight support, and can be better It shows the continuity and abruptness of the frequency domain signal, and the effect is better in practical engineering applications. Therefore, DB wavelet is used here to perform 4-level decomposition and reconstruction of EEG signals. Filter out the DC component or slow baseline drift in the EEG signal. Select DB2 wavelet, at this time M=3, and the low-pass filter coefficients (scale function coefficients) are as follows:

Because floating-point numbers are more complicated to implement in FPGA, in order to reduce the amount of calculation and resources of FPGA, filter calculation can be converted into integer operation and shift operation. For this reason, the above filter coefficients need to be converted into integers. For each filter The coefficient is quantized with a 16-bit word length, that is, multiplied by 215 and then taken as an integer, and the output signal of the filter is shifted by 15 bits to get the actual output.

With DSP Builder as the platform, system-level modeling and simulation of the formula (7), formula (8) and formula (13) algorithms are carried out, and then the Signal Compiler is used to generate HDL files, and then the Quartus II is used for timing simulation verification.

3.1 DSP Builder realizes lD-DWT decomposition

The structure of the decomposition module is shown in Figure 1. The signal is output from the 4-stage delay line in parallel, convolved with the FIR filter coefficients, and then even decimated to obtain the approximate part and the detailed part. The secondary decimation module uses the down-sampling module of DSP Builder, and uses Signal Compiler to generate HDL files.

Application Design of Wavelet Transform System Based on FPGA

In order to reduce the hardware resources consumed by the system, the lower 8 bits of the output result are discarded to ensure that the signal maintains the same energy level before and after decomposition. It can be seen from Figure 1 that each sub-module works in parallel without any cross signals between the sub-modules, and data is transmitted backwards from the input end in a pipeline manner, realizing real-time pipeline work. The design principle of the two-level decomposition module is the same as the one-level decomposition module.

3.2 DSP Builder realizes 1D-DWT reconstruction

From the Mallat algorithm, the structure of the reconstruction module is shown in Figure 2. First, the signal is twice interpolated, and then the signal is output from the four-stage delay line in parallel, and is convolved with the FIR filter coefficients. The difference from decomposition is that the reconstruction has two signal inputs, which are filtered in parallel with FIR after four-stage delay. After convolution by the processor, the results obtained are superimposed to obtain the reconstructed signal, and then the Signal Compiler is used to generate the HDL file, and the reconstruction module also works in a pipeline mode. The secondary capture module is implemented by the up-sampling module of DSP Builder.

Application Design of Wavelet Transform System Based on FPGA

4 Simulation and design

Select a set of original data[1234567891011…]at the same time as the input signal, using the HDL file generated in Figure 1, timing in the Quartus II environment Simulation, Figure 3 shows the first-level wavelet decomposition time series simulation waveform. Using the HDL file generated in Figure 2 and using the low-frequency and high-frequency output results of Figure 3 as the reconstruction input data, a first-level wavelet reconstruction simulation is performed. The simulation waveform is shown in Figure 4. It can be seen from Figure 3 and Figure 4 that, except for the delay in the reconstructed waveform, the reconstructed waveform has no distortion and can perfectly reconstruct the original signal, that is, the input and output satisfy q(n)=xin(n-k).

Application Design of Wavelet Transform System Based on FPGA

Use wavelet transform’s multi-scale decomposition and reconstruction method to filter out certain components of the signal (high frequency or low frequency), use DB2 wavelet to carry out four-level wavelet packet decomposition of EEG signals, according to the principle of wavelet packet decomposition, cascade one-level decomposition Module, each time a string of input data is reduced to half of the original one after decomposing. The frequency division module is used to control the clock signals at all levels, and the frequency division module is written and generated by VHDL language. Synchronously output 3 clock signals, which are used as the clock input signals for the next three stages of decomposition. Then the decomposed output signal is reconstructed by four-level wavelet packet, processed in the same way, and the first-level reconstruction module is cascaded, and the output data is doubled every time it is reconstructed. Try to use a phase-locked loop to control the clock signals at all levels. The phase-locked loop is implemented by the functional module that comes with Quartus II, and outputs 3 multiplied clock signals at the same time as the input clock signal for the post-i-level reconstruction part.

5 Conclusion

Use the wavelet packet of the signal to decompose the high-resolution time-frequency relationship. In the filtering part, a causal filter is selected to filter the EEG signal in real time. On the DSP Builder platform, combined with Mallat algorithm and modular design principles, the FPGA-based pipeline structure wavelet transform system is designed. This top-down highly modular design method makes the system upgrade and change quite convenient. The design of FPGA wavelet transform system applied to real-time filtering of EEG signals is a future research direction.

The Links:   KCG047QV1AAG02 2SAR544P5T100 LCDDISPLAY

Scroll to top