David Patterson: RISC-V will be the most important instruction set in the world

A decade ago, an idea was born in a lab at the University of California, Berkeley, who created a general language for computer chips, a set of instructions that they envisioned would be used by all chip makers, not part of any company.

It wasn’t meant to be an impressive new technology, it just wanted to put the entire industry on the same page to simplify chip manufacturing to drive things forward.

But an interesting thing happened on the way to a global chip standard: RISC-V has begun to produce some technological breakthroughs in chip design, just as Berkeley has done.

To name just one example, recent microprocessor designs using RISC-V have reached clock speeds of 5 GHz, much higher than the latest Intel top-of-the-line Xeon server chip E7 running at 3.2 GHz. However, the new RISC-V chips consume only 1 watt at 1.1 volts, less than one percent of the power consumed by Intel Xeons.

RISC-V’s speed and power efficiency also surpassed the specifications of Exynos 4, Samsung Electronics’ top-of-the-line product for its smartphones, which is based on computing cores provided by Intel’s main rival, ARM Holdings Plc.

“It’s pretty surprising, because I think IBM mainframes with a 5GHZ frequency should require liquid cooling and consume 100 watts,” David Patterson, a professor at the University of California, Berkeley, told ZDNet.

To Patterson’s surprise, technological innovation was on the rise. “The potential for innovation is always there,” he said, but when he and Berkeley colleague Krste Asanović first wrote the manifesto for RISC-V in 2011, that wasn’t their main expectation.

“I think one of the things that’s going to happen is because it’s open, we’re going to see all this competition,” he said.

“Maybe because of all the competition, we’re starting to see some really interesting perspectives in the design space,” Patterson said.

This prototype of the new 5 GHz processor was not created by a startup. It is made by Micro Magic Inc., a Silicon Valley intellectual property design company that has worked with all the big Silicon Valley companies for 25 years. The ability of a small but experienced chip designer to accomplish the task suggests that a design renaissance may be on the horizon.

The Embedded Benchmark Microprocessor Consortium records that not only is the chip faster with less power, but it also scores higher than Intel on a benchmark score of raw CPU performance called CoreMark and Samsung. The RISC-V chip scored 13,000, more than double the performance-per-core score of the ARM-based Exynos. Although the Intel Xeon’s per core is nominally higher at 26,009, the Xeon part requires 120 more execution threads to reach that performance.

Dr. Andy Huang, a longtime chip industry executive, serves as Micro Magic’s business liaison. The breakthrough, he explained to ZDNet in a phone interview, is in the way the CPU and memory interact. Micro Magic’s two founders, Mark Santoro and Lee Tavrow, patented the SRAM computer memory chip in the early ’90s, the fastest such memory ever.

The RISC-V prototype removes the bottlenecks that can exist with fast memory and slow chips.

“If the memory runs at 5 GHz and the logic runs at 1 GHz, where is the bottleneck?” Huang smiled, but didn’t reveal details.

The point, Huang said, is that because RISC-V is open, unlike the complex instruction set architecture of Intel chips or even the version of RISC found in ARM chips, RISCV can address this bottleneck through chip design. Not possible if the chip’s instructions are locked.

The analogy he uses is Android vs iOS.

“I asked my son why he liked Samsung (smartphone) more than Apple and he said it was because if he wanted to change something, he could ask one of his programming friends to do it for him, because Android is open, unlike iOS different,” Huang said.

“That’s why we attribute all our success to Dr. Patterson,” Huang said. “He has created the most efficient and elegant RISC architecture to date.”

“We should call him Saint Patterson,” Huang said.

The ability to tinker with the instruction set is just part of what Micro Magic is showing. There are economic factors at play.

Dr. Huang emphasized that, unlike CISC or ARM, which each have more than 1,000 instructions, RISC-V’s instruction set is less than a hundred.

Because of the simplicity of the RISC-V instruction set, Micro Magic is able to produce chips using standard silicon wafers without special adjustments. This makes it possible to use what’s called a shuttle run, where chips are grouped together on the same wafer as someone else’s chips during the manufacturing process. This can be much cheaper because the cost of the wafer is shared in many ways.

“People talk about spending $100 million to customize an ASIC,” Patterson noted. “Well, they didn’t spend $100 million to do it,” Patterson said of Micro Magic.

Although not emphasized by Patterson and Huang, there is a second factor at play. If you don’t pay the overhead of an ARM license, it’s much easier to use shuttle run, which then has to be amortized over many parts.

In a sense, RISC-V could facilitate the micro-batch production methods seen in many modern product lines, from breweries to cheese to clothing.

The question of economics is contentious, considering that Nvidia, one of the world’s largest chipmakers, is buying ARM for $40 billion. The sale will allow Nvidia to receive royalties from ARM’s intellectual property and set a roadmap for the world’s most widely used chip instructions.

Nvidia CEO Jensen Huang described his ambitious plans for ARM, and he assured Wall Street that ARM’s licensees, his rivals, wouldn’t mind him buying the biggest supplier.

But the move clearly opens up new opportunities for alternatives. When asked about the deal, Patterson responded cautiously. Because Nvidia is a member of the RISC-V ecosystem and supports the technology wholeheartedly.

“I think people tend to think of RISC-V as just an academic idea,” Patterson told ZDNet. “Then, when it proves that proprietary instruction sets can be bought and sold, that becomes yet another reason for an open architecture.”

Micro Magic’s Huang said he has attracted interest from tech giants since Micro Magic made its brief chip announcement.

“I have received emails from two listed companies,” Huang said, without giving his name.

Huang offers a hypothetical scenario in which Apple or Google could use the chip to make a breakthrough in power consumption.

“Google already has Android, the mobile open source software, and think about how it would benefit all mobile customers if they also had the most power-efficient, high-performance open-source RISC core,” Huang told ZDNet.

“Imagine the latest Apple Watch not having to charge overnight,” Huang said.

With or without such a big deal, Micro Magic hopes to incorporate its RISC-V intellectual property into more and more designs to have a material impact on global electricity usage, Huang said.

“Our intent with this IP is to help the world, to help the world of PCs, the world of laptops, the world of tablets, the world of mobile phones, wearables, gaming, electric vehicles and IoT – whatever you name it, our goal is to bring the world’s carbon Emissions are cut in half.”

A prototype CPU is not revolutionary. Comparisons with actual shipments from Intel and others reveal the fact that many more parts are required to complete the chip design.

This is where the ecosystem of companies around RISC-V becomes important. The number of announced companies announcing that they will use RISC-V is small but growing.

“Everything you can think of, right down to the data center, people are seriously considering RISC-V right now,” Patterson said.

“In a sense, we’ve come to an end,” he said, “from why would I use RISC-V a few years ago, to why would I not use RISC-V?”

Prominent among the ecosystem parties is SiFive, a Silicon Valley-based startup that has specialized in developing chip intellectual property based on RISC-V for many years. In August, the company launched a business unit dedicated to producing custom chips for a variety of applications, including AI and edge computing, called OpenFive. Patterson’s collaborator, Professor Asanovi?, is the chief architect of SiFive.

Another is embedded processor maker Andes Technology of Taiwan, which has sold billions of CPU designs to electronics makers over the years.

Last month, both SiFive and Andes Technology showcased new chip designs for AI using RISC-V at the Linley Fall Processor Conference, a well-known chip technology conference.

SiFive told ZDNet that it has now won more than 200 design orders from more than 80 companies, including six of the top ten semiconductor manufacturers. SiFive told ZDNet: “SiFive currently ships tens of millions of cores with Design Win from FADU, Huami, Qualcomm, Samsung and Synaptics.”

Andes told investors in its quarterly report this month that about a third of its revenue this year came from RISC-V-based parts.

Seagate Technology Corp. and large disk-drive maker Western Digital Corp. are both sponsors of next month’s RISC-V Summit, the ecosystem’s third annual technology conference. The event was sponsored by the RISC-V International Association, a non-profit corporation that currently represents more than 750 parties working to advance the standard, including Chinese smartphone maker Huawei, chipmakers Xilinx and Qualcomm, and IBM. Asanovi? is the chair of the group, and Patterson is the vice-chair.

But no matter how successful RISC-V is, the world may never know the full scope of its usage. That’s because, while ARM and other commercial technology providers are signing documents with their licensees, no one is using RISC-V to disclose usage.

RISC-V International requires suppliers to voluntarily disclose usage, but does not compel such disclosure.

As a result, Patterson said, “it’s hard to see concrete evidence” of the extent of RISC-V’s use.

Still, evidence of technological advances in products such as Micro Magic suggests to Patterson and others that the impact of RISC-V could ultimately be significant.

Recently, Patterson conducted a series of one-on-one interviews with collaborators via video to virtually celebrate the tenth anniversary of RISC-V.

Patterson told ZDNet that a collaborator made a surprising point.

“In five to ten years, RISC-V could be the most important instruction set in the world,” recalls Patterson. “On the one hand, it sounds crazy, but it’s not impossible,” he said.

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