Keil Nuvoton NUC140VE3AN ARM MCU development program

Nuvoton’s NUC140VE3AN is a full-speed USB 2.0 and CAN function, embedded Cortex™-M0 core, MCU running up to 50MHz, integrated 32K/64K/128K byte Flash memory, and 4K/8K /16K bytes of SRAM, 4K bytes of ROM for storing ISP boot codes, and 4K bytes of data Flash memory. There are also rich peripherals, such as timers, watchdog timers, RTC, PDMA, UART, SPI, I2C, I2S, PWM timers, GPIO, LIN, CAN, PS/2, USB 2.0 FS devices, 12 Bit ADC, analog comparator, low-voltage reset control and under-voltage detection functions, mainly used in industrial control, data communication, USB applications and motor control, automotive and consumer products. Keil’s MCBNUC1xx evaluation board can evaluate and test based on ARM Cortex™-M0 Nuvoton NUC1xx series processor features and working procedures. This article introduces the main features of NuMicro NUC140, block diagram, MCBNUC1xx evaluation board main features, block diagram and circuit diagram.

NuMicro™ NUC140 Connectivity Line with full-speed USB 2.0 and CAN functions, embedded Cortex™-M0 core, can run up to 50 MHz, built-in 32K/64K/128K bytes of Flash memory, and 4K/8K/16K bytes of SRAM , 4K bytes are used to store the ROM of the ISP boot code, and 4K bytes of data Flash memory. There are also rich peripherals, such as timers, watchdog timers, RTC, PDMA, UART, SPI, I2C, I2S, PWM timers, GPIO, LIN, CAN, PS/2, USB 2.0 FS devices, 12 Bit ADC, analog comparator, low-voltage reset control and under-voltage detection function.

Main features of NuMicro™ NUC140:

• Kernel

ARM® Cortex™-M0 core runs up to 50 MHz

-A 24-bit system timer

-Support low-power sleep mode

– Single-cycle 32-bit hardware multiplier

– Nested Vectored Interrupt Controller (NVIC) is used to control 32 interrupt sources, each interrupt source can be set to 4 priority levels

– Support serial wire debugging (SWD) with 2 observation points/4 breakpoints

• Built-in LDO, wide voltage working range 2.5 V to 5.5 V

• Flash memory

– 32K/64K/128K byte Flash is used to store program code

– 4KB flash is used to store ISP boot code

-Support in-system programming (ISP) way to update applications

– Support 512-byte single page erase

– The data FLASH address and size can be configured in the 128K byte system, and it is fixed to 4K byte data in the 32K byte and 64K byte system

– Support 2-wire ICP upgrade method through SWD/ICE interface

– Supports parallel high-speed programming mode of external programmer

• SRAM memory

– 4K/8K/16K bytes built-in SRAM

– Support PDMA mode

• PDMA (Peripheral DMA)

– Support 9-channel PDMA for automatic data transmission of SRAM and peripheral devices

• Clock control

– Flexible clock selection for different applications

– The internal 22.1184 MHz high-speed oscillator can be used for system operation

? At +25 ℃, VDD = 5.0 V, the accuracy is corrected to ± 1%

? Within the range of -40 ℃ ~ +85 ℃ and VDD = 2.5 V ~ 5.5 V, the accuracy is ± 3%

– The internal low-power 10 KHz low-speed oscillator is used for functions such as watchdog and wake-up from power-down mode

– Support a set of PLL, up to 50 MHz, for high-performance system operation

– External 4~24 MHz crystal oscillator input for USB and precise timing operation

– External 32.768 kHz crystal oscillator input for RTC and low power mode operation


– Four I/O modes:

 Quasi-two-way mode

 Push-pull output mode

 Open drain output mode

 High-impedance input mode

-TTL/Schmitt trigger input optional

– I/O pins can be configured as interrupt sources in edge/level trigger mode

– Support high current drive and sink I/O mode

• Timer

– Support 4 groups of 32-bit timers, each timer has a 24-bit up-counting timer and an 8-bit prescaler counter

– Each timer has an independent clock source

– Provide one-shot, periodic, toggle and continuous counting operation modes

-Support event counting function

-Support input capture function

• Watchdog Timer

– Multiple clock sources

– There are 8 optional time-out periods from 1.6ms to 26.0sec (depending on the selected clock source)

– WDT can be used as a wake-up in power-down mode/sleep mode

-Interrupt/reset selection for watchdog timer overflow


– Support software frequency compensation function through frequency compensation register (FCR)

-Support RTC counting (seconds, minutes, hours) and perpetual calendar functions (day, month, year)

-Support alarm register (second, minute, hour, day, month, year)

– Optional 12-hour clock or 24-hour clock

– Automatic leap year recognition

– Support cycle time tick interrupt, including 8 selectable cycles 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second

– Support wake-up function

• PWM/Capture

– Built-in four 16-bit PWM generators, which can output 8 PWMs or 4 sets of complementary paired PWMs

– Each PWM generator is equipped with a clock source selector, a clock divider, an 8-bit clock prescaler and a dead zone generator for complementary paired PWM

– 8 channels of 16-bit capture timers (shared PWM timers) provide 8 channels of input rising/falling edge capture function

-Support capture interrupt


– Up to three groups of UART controllers

– Support flow control (TXD, RXD, CTS and RTS)

– UART0 with 64-byte FIFO for high-speed mode

– UART1/2 (optional) with 16-byte FIFO for standard mode

– Support IrDA (SIR) and LIN functions

– Support RS-485 9-bit mode and direction control

– Programmable baud rate generator frequency up to 1/16 system clock

– Support PDMA mode


– Support up to 4 groups of SPI controllers

– The host speed is as high as 32 MHz, and the slave is as high as 10 MHz (when the chip is working at 5V)

– Support SPI master/slave mode

– Full-duplex synchronous serial data transmission

– Variable data length (from 1 bit to 32 bit) transmission mode

Can set MSB or LSB first transmission mode

– Whether to receive or transmit on the rising or falling edge of the clock is independently configured

– 2 slave chip select lines when used as a master, 1 slave chip selection when used as a slave

– Support byte sleep mode in 32-bit transmission mode

– Support PDMA mode

– Support three-wire two-way interface without slave selection signal

• I2C

– Support up to 2 groups of I2C devices

– Master/Slave mode

– Two-way data transmission between master and slave

– Multi-host bus support (no central host)

– Arbitration of data transmission between multiple hosts at the same time to avoid serial data damage on the bus

– The bus adopts a serial synchronous clock, which can realize transmission between devices at different rates

– The serial synchronous clock can be used as a handshake method to control the suspension and resume transmission of data on the bus

– Programmable clock is suitable for different rate control

– Support multiple address recognition on I2C bus (4 slave addresses with mask option)

• I2S

– External audio CODEC interface

-Can be used as master or slave mode

– Can handle 8, 16, 24 and 32 bit words

– Support mono and stereo audio data

– Support I2S and most significant bit data format

– Provides two sets of 8-word FIFO data buffers, one set for sending and one set for receiving

– When the buffer exceeds the programmable boundary, an interrupt request is generated

– Supports two groups of DMA requests, one for sending and the other for receiving

• CAN 2.0

– Support CAN 2.0A and 2.0B protocol

– Bit transfer rate up to 1M bit/s

– 32 message objects

– Each message object has its own identifier mask

– Programmable FIFO mode (link message object)

-Maskable interrupt

– Disable automatic retransmission mode in time-triggered CAN applications

– Support power-down mode wake-up function

• PS/2 device controller

-Prohibit Host communication and request sending detection

– Receive frame error detection

-Programmable 1 to 16 bytes send buffer to reduce the burden on the CPU

– Double buffering of data received

– Software controllable bus

• USB 2.0 Full-Speed ​​Device

– A set of 12Mbps USB 2.0 FS device

– On-chip integrated USB transceiver module

– Provide 1 set of interrupt sources and four interrupt events

Support control transmission (Control), bulk transmission (Bulk In/Out), interrupt transmission (Interrupt) and synchronous transmission. When there is no signal on the bus for 3ms, it has the function of automatic suspension

– Support 6 groups of programmable endpoints (endpoints)

– 512 bytes of internal SRAM as USB buffer area

– Support remote wake-up function

• Support EBI (External Bus Interface) (100-pin and 64-pin Package Only)

Accessible space: 64KB in 8-bit mode or 128KB in 16-bit mode

– Support 8-bit/16-bit data width

– Support byte write in 16-bit data width mode


– 12-bit ADC, conversion rate up to 700K SPS

– Up to 8 channels of single-ended mode input or 4 channels of differential mode input

– Single scan mode/single cycle scan mode/continuous scan mode

– Each channel has an independent result register

– Scan enable channel

– Threshold voltage detection

-Software programming or external pin trigger to start conversion

– Support PDMA mode

• Analog Comparator

– 2 sets of analog comparator modules

– The negative terminal potential can be selected from external input or internal band gap voltage

– The change of the comparison result can be used as an interrupt trigger condition

– Support power-down mode wake-up function

• Built-in temperature sensor, 1℃ resolution

• Brown-Out detector

– Support four-level detection voltage: 4.5 V/3.8 V/2.7 V/2.2 V

– Support under-voltage interrupt and reset options

• Low voltage reset

– Threshold voltage: 2.0 V

• Working temperature: -40℃~85℃

• Package:

– Lead-free package (RoHS)

LQFP 100-pin / 64-pin / 48-pin

NuMicro™ NUC140 Connectivity Line Selection Guide
Keil Nuvoton NUC140VE3AN ARM MCU development program
Keil Nuvoton NUC140VE3AN ARM MCU development program
Figure 1. Block diagram of NuMicro™ NUC140

NUC140VE3AN application:

Industrial Control

Data Communications

USB Applications

Consumer Products

Motor Control

Keil Nuvoton NUC140VE3AN ARM MCU development program
Figure 2. Outline drawing of MCBNUC1xx evaluation board

The Keil MCBNUC1xx Evaluation Board enables you to create and test working programs based on the Nuvoton NUC1xx family of ARM Cortex™-M0 processor-based devices.

Main features of MCBNUC1xx evaluation board:

50MHz NUC140VE3AN ARM Cortex™-M0 processor-based MCU in 100-pin LQFP

On-Chip Memory: 128KB Flash & 16KB RAM

USB 2.0 Full Speed ​​Device Interface

UART, I2C, SPI and 76 GPIO via PCB headers

Potentiometer for ADC Input

8 LEDs and 3 push-buttons

Power via USB connector

Debug Interface Connectors

10-pin Cortex debug (0.05 inch connector)

20-pin ARM Standard JTAG (0.1 inch connector)

MCBNUC1xx evaluation board technical indicators:




MCU Vendor






ARM Processor


MCU Clock


Prototyping Area

Keil Nuvoton NUC140VE3AN ARM MCU development program


4.0 x 2.75


100 x 70


On-Chip RAM





Push Buttons


I/O Port LEDs


Analog Input

Keil Nuvoton NUC140VE3AN ARM MCU development program

Debug Interface

JTAG Interface

Keil Nuvoton NUC140VE3AN ARM MCU development program

SWD Interface

Keil Nuvoton NUC140VE3AN ARM MCU development program

10-pin Cortex Connector

Keil Nuvoton NUC140VE3AN ARM MCU development program

20-pin JTAG Connector

Keil Nuvoton NUC140VE3AN ARM MCU development program







~ 15 mA


~ 20 mA

The hardware block diagram displays the input, configuration, power system, and User I/O on the board. This visual presentation helps you to understand the MCBNUC1xx board components.

Keil Nuvoton NUC140VE3AN ARM MCU development program
Figure 3. Block diagram of MCBNUC1xx evaluation board
Keil Nuvoton NUC140VE3AN ARM MCU development program

Figure 4. MCBNUC1xx evaluation board circuit diagram
For details, see:

The Links:   LB040Q02-TD05 LM215WF3-SLC2

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