The working principle of frame synchronization system and how to realize its design based on FPGA

In digital communication, a certain number of symbols are generally composed of “words” or “sentences”, that is, “frames” for transmission. Therefore, the frequency of the frame synchronization signal is easily obtained by dividing the frequency of the bit synchronization signal. But the beginning and end of each frame cannot be determined by the output of the divider. To this end, the task of frame synchronization is to give the “beginning” and “end” moments. There are usually two ways to extract the frame synchronization signal: one is to insert some special code groups in the information flow as the head and tail marks of each frame.

1 Introduction

In digital communication, a certain number of symbols are generally composed of “words” or “sentences”, that is, “frames” for transmission. Therefore, the frequency of the frame synchronization signal is easily obtained by dividing the frequency of the bit synchronization signal. But the beginning and end of each frame cannot be determined by the output of the divider. To this end, the task of frame synchronization is to give the “beginning” and “end” moments. There are usually two ways to extract the frame synchronization signal: one is to insert some special code groups in the information flow as the head and tail marks of each frame. The other type does not need to join the code group, but uses the different characteristics of the data code groups to achieve synchronization. The first method is adopted here – continuous insertion method to achieve frame synchronization. The so-called continuous insertion method is to insert the frame synchronization code at the beginning of each frame. The frame synchronization code used is Barker code. Barker code is a kind of aperiodic sequence with special regularity. Its local autocorrelation function has sharp single peak characteristics. . Therefore, the FPGA design and implementation of the frame synchronization system is proposed here.

2. The working principle of the frame synchronization system

The key to realizing frame synchronization is to extract the synchronization code from a frame-by-frame data stream. One frame of signal code designed in this design is composed of 39-bit symbols. Among them, the Barker code is 1110010 seven-bit code, and the data code is composed of 32-bit symbols. Only when the receiver receives a frame of signal, will the synchronization signal be output. The design block diagram of the frame synchronization system is shown in Figure 1.

  The working principle of frame synchronization system and how to realize its design based on FPGA

The frame synchronization system working state is divided into capture state and maintenance state. When the synchronization is not established, the system is in the capture state, and the Q terminal of the state trigger is low level. Once the identifier outputs a pulse, since the Q terminal is high level, the AND gate 1 outputs “1” through the OR gate, and at the same time, the OR gate makes the output “1”. The output of AND gate 3 is also “1”, which clears the frequency division counter module. And gate 1 outputs all the way to the S terminal of the flip-flop, the Q terminal becomes a high level, and the gate 4 is opened, and the frame synchronization output pulse. The system changes from the capture state to the hold state, and the frame synchronization is established.

After the frame synchronization is established, the system is in the hold state. If the frequency divider outputs the frame synchronization pulse at this time, but the identifier does not output, it may be that the system is really out of synchronization, or it may be caused by accidental interference, so a protection circuit is added to the circuit. The protection circuit is also a frequency division counter. Only when the frame synchronization signal cannot be received several times in a row, the system will consider that the synchronization state is lost. Since the probability of losing synchronization is very small, the system sets the frequency division counter value to 5. That is to say, if the frame synchronization signal is not received for 5 consecutive frames, the system considers that the synchronization state is lost. Of course, the frequency division value can be set to other values, but the larger the value is, the greater the probability of missed identification in the synchronization maintaining state is. One output of AND gate 1 is set to the enable terminal of the 5-frequency divider to start counting. When the count is full, a pulse will be output to set the state flip-flop to zero, so that no frame synchronization signal is output, and the synchronization circuit enters the capture state again.

3. Modeling and realization of frame synchronization circuit functional modules

3.1 Barker code identification module

The function of this module is to identify the frame synchronization code Barker code from the data stream. The recognizer module is shown in Figure 2.

The working principle of frame synchronization system and how to realize its design based on FPGA

The first part of the module ZCB in Figure 2 mainly completes the serial-parallel conversion and shift functions, which are realized by 7 D flip-flops and 3 NOT gates. The second part of the module AND7 function: only when the Barker code 1110010 is input accurately, the output of the recognizer will be “1”. Because the output Barker code identification signal will directly affect the subsequent synchronization protection circuit, only by accurately outputting the Barker code can false synchronization be avoided. AND7 can identify Barker codes concisely and accurately. Figure 3 is a simulation diagram of the Barker code identification module, in which bakeshibie is the output of the recognizer; fenpin39 is the output of the 39-frequency counter; zin is the input data; zclk is the clock signal.

The working principle of frame synchronization system and how to realize its design based on FPGA

3.2 Frequency division counter module

This design uses 2 frequency division counters with clearing, which are 39 frequency division counters and 5 frequency division counters. Among them, the 39-frequency counter can meet the requirements of 7-bit Barker code + 4-byte data. When the 39 frequency divider outputs a pulse, the discriminator should also output a pulse. As long as its phase corresponds to the output, the frame synchronization signal can be extracted.

The simulation diagram of the 39-frequency counter is shown in Figure 4, where clk is the clock signal terminal; clr is the clock clearing terminal; output is the output terminal.

The working principle of frame synchronization system and how to realize its design based on FPGA

3.3 Synchronization protection module

When the system enters the maintenance state, the synchronization protection circuit is required to protect the frame synchronization signal. This part of the circuit is composed of a clock control module, a basic RS flip-flop module and a 5-frequency counter. Among them, the main functions of the clock control module and the basic RS flip-flop module are state transition and control output frame synchronization pulse. It is worth noting that for the RS flip-flop: if R=0 and S=”0 and then a change from 0 to 1 occurs at the same time”, then the output terminals Q and Q must be converted from 1 to 0, and the output of Q and Q terminals will be For arbitrary state, this is the phenomenon of risk-taking competition. When risk competition occurs, since the output of the flip-flop is in an arbitrary state, the output of the entire system will be in an arbitrary state. The solution is to add a clock control module to the system to control the reset end of the flip-flop to ensure that no arbitrary state occurs and to make the system work in a stable state. When the divider by 5 has no output from the recognizer module, this may be caused by the real out-of-sync of the system or occasional interference. Only in this case will the system truly consider out-of-sync for 5 consecutive times. The simulation diagram of the protection module is shown in Figure 5, where zhengout is the frame synchronization output signal; clk is the clock signal; data is the input signal code; q is the Q end of the RS flip-flop;

The working principle of frame synchronization system and how to realize its design based on FPGA

4. Top-level file design of frame synchronization system

The so-called top-level file design is to put all the modules involved together to form an easy-to-read graphical way. When compiling each module, if there is no error in the design. The system creates a symbol file representing the module, which can be called by the high-level design. In this design, each module is designed through VHDL language and compiled under the Quartus II development software. Adopt the EP1C12Q240C8 device of Altera’s Cvclone series, and the frame synchronization circuit only uses less than 1% of the logic cells of the device. The top-level design graphics are shown in Figure 6. In Figure 6, ZCB and AND7 (seven-input AND gate) are Barker code identifiers; CLKCONTR is a clock controller; FENPIN5 is a 5 divider counter; FENPIN39 is a 39 divider counter; RS_CLK is an RS flip-flop.

The working principle of frame synchronization system and how to realize its design based on FPGA

Analysis of experimental results: In the Quartus II environment, the period of the clock clk is 200μs. When the value of the clock period is very small, such as nanosecond level, the system is prone to risk competition. Therefore, the value of the clock period should be set. larger. data is the input data stream. In order to facilitate the simulation, only 3 groups of Barker codes are added to the data stream. bakeshibie is the output of the Barker code recognizer. When the Barker code appears, the Q terminal of the flip-flop becomes a high level, and the system enters the maintenance state. At this time, the 5-frequency counter starts to count. If the Barker code is detected, the divide-by-5 ​​counter starts counting again. If the Barker code does not appear after 5 counts, the system completely loses the synchronization state, the Q terminal becomes low level, and the system enters the capture state. The overall design timing simulation diagram is shown in Figure 7. Since this frame synchronization system is to be used in DPSK demodulation, the clock frequency of frame synchronization system simulation should be consistent with the clock frequency of DPSK demodulation. When simulating, pay attention to the transmission direction of the symbol, that is, whether the Barker code is sent with high bits first or low bits first, which will affect the quality of the simulation.

The working principle of frame synchronization system and how to realize its design based on FPGA

5 Conclusion

The function of each module, the implementation method and the simulation graphics are explained in detail. The system strictly restricts the frame synchronization code (Barker code), that is, the system will only output the frame synchronization signal after the frame synchronization code is strictly received, which improves the reliability of the system. The protection circuit design effectively reduces the probability of missed synchronization and false synchronization, and the clock-controlled RS flip-flop ensures the correct transition of the synchronization system state. All technical indicators of the synchronization system meet the requirements, work correctly and reliably, and have high use value.

The Links:   NL128102AC31-02A NL6448BC20-14

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